User guide

Port Direction Clock Domain Description
tx_serial_clk0 / tx_
serial_clk1
In N/A
The high speed serial clock generated
by the PLL.
Note: For Gen3 x1 ONLY tx_serial_
clk1 is used.
pipe_hclk_in In N/A
The 500 MHz clock used for the ASN
block. This clock is generated by the
PLL, configured for Gen1/Gen2.
Note: For Gen3 designs, use from the
fPLL that is used for Gen1/Gen2.
pipe_hclk_out Out N/A
The 500 MHz clock output provided
to the PHY - MAC interface.
PIPE Input from PHY - MAC Layer
tx_parallel_data[31:0],
[15:0], or [7:0]
In tx_coreclkin
The TX parallel data driven from the
MAC. For Gen1 this can be 8 or 16
bits. For Gen2 this is 16 bits. For Gen3
this is 32 bits.
Note: unused_tx_parallel_data
should be tied to '0'.
Active High
tx_datak[3:0], [1:0], or
[0]
In tx_coreclkin
The data and control indicator for the
transmitted data.
For Gen1 or Gen2, when 0, indicates
that tx_parallel_data is data, when
1, indicates that tx_parallel_data is
control.
For Gen3, bit[0] corresponds to tx_
parallel_data[7:0], bit[1]
corresponds to tx_parallel_
data[15:8], and so on.
Active High
UG-01143
2015.05.11
Native PHY IP Ports for PIPE
2-255
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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