User guide

Native PHY IP Ports for PIPE
Figure 2-90: Signals and Ports of Native PHY IP for PIPE
-
reconfig_reset
reconfig_clk
reconfig_avmm
tx_digitalreset
tx_datak
tx_parallel_data
tx_coreclkin
tx_clkout
pipe_rx_elecidle
pipe_phy_status
pipe_rate
pipe_g3_tx_deemph
pipe_g3_rxpresethint
pipe_sw_done
pipe_rx_polarity
pipe_tx_elecidle
pipe_tx_detectrx_loopback
Gen1/Gen2/Gen3 - Black
Gen2/Gen3 - Red
Gen3 Blue
pipe_powerdown
pipe_rx_eidleinfersel
pipe_tx_sync_hdr
pipe_tx_data_valid
pipe_tx_blk_start
pipe_tx_deemph
tx_bonding_clocks
pipe_rx_data_valid
pipe_rx_blk_start
pipe_rx_sync_hdr
tx_analogreset
rx_analogreset
rx_digitalreset
rx_datak
rx_parallel_data
rx_clkout
rx_coreclkin
rx_syncstatus
tx_datak
tx_parallel_data
tx_coreclkin
tx_clkout
unused_tx_parallel_data[118:0]
Reconfiguration
Registers
TX Standard PCS
PIPE Interface
rx_datak
rx_parallel_data
rx_clkout
rx_coreclkin
rx_syncstatus
unused_rx_parallel_data[118:0]
RX Standard PCS
Nios II Hard
Calibration IP
TX PMA
Serializer
RX PMA
Deserializer CDR
tx_cal_busy
rx_cal_busy
tx_serial_data
pipe_hclk_out
pipe_hclk_in (from TX PLL)
pipe_tx_compliance
pipe_tx_margin
pipe_tx_swing
pipe_rx_valid
pipe_rx_status
pipe_sw
rx_serial_data
rx_cdr_refclk0
rx_is_lockedtodata
rx_is_lockedtoref
10
10
tx_serial_clk0 (from TX PLL)
Arria 10 Transceiver Native PHY
-
Local CGB
(for X1
Modes Only)
Table 2-162: Ports for Arria 10 Transceiver Native PHY in PIPE Mode
Port Direction Clock Domain Description
Clocks
rx_cdr_refclk0 In N/A
The 100/125 MHz input reference
clock source for the PHY's TX PLL
and RX CDR.
2-254
Native PHY IP Ports for PIPE
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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