User guide

Signal Name Gen1 (TX Byte
Serializer and
RX Byte
Deserializer
disabled)
Gen1 (TX Byte
Serializer and RX
Byte Deserializer
in X2 mode), Gen2
(TX Byte Serializer
and RX Byte
Deserializer in X2
mode)
Gen3
pipe_rx_status rx_
parallel_
data[69:67]
rx_parallel_
data[69:67]
rx_parallel_data[69:67]
pipe_tx_deemph
N/A
tx_parallel_
data[52]
N/A
pipe_tx_sync_hdr N/A N/A tx_parallel_data[55:54]
pipe_tx_blk_start N/A N/A tx_parallel_data[56]
pipe_tx_data_valid N/A N/A tx_parallel_data[60]
pipe_rx_sync_hdr N/A N/A rx_parallel_data[71:70]
pipe_rx_blk_start N/A N/A rx_parallel_data[72]
pipe_rx_data_valid N/A N/A rx_parallel_data[76]
Note: The signals in the left-most column are automatically mapped to a subset of a 128-bit
tx_parallel_data word when the Simplified Interface is enabled.
UG-01143
2015.05.11
Native PHY IP Parameter Settings for PIPE
2-253
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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