User guide

Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE
Enable TX bit reversal Off Off Off
Enable TX byte reversal Off Off Off
Enable TX polarity inversion Off Off Off
Enable tx_polinv port Off Off Off
Enable RX bit reversal Off Off Off
Enable rx_std_bitrev_ena
port
Off Off Off
Enable RX byte reversal Off Off Off
Enable rx_std_byterev_ena
port
Off Off Off
Enable RX polarity inversion Off Off Off
Enable rx_polinv port Off Off Off
Enable rx_std_signaldetect
port
Optional Optional Optional
PCIe Ports
Enable PCIe dynamic datarate
switch ports
Off Enabled Enabled
Enable PCIe pipe_hclk_in
and pipe_hclk_out ports
Enabled Enabled Enabled
Enable PCIe Gen3 analog
control ports
Off Off Enabled
Enable PCIe electrical idle
control and status ports
Enabled Enabled Enabled
Enable PCIe pipe_rx_
polarity port
Enabled Enabled Enabled
Table 2-161: Bit Mappings When the Simplified Interface Is Disabled
Signal Name Gen1 (TX Byte
Serializer and
RX Byte
Deserializer
disabled)
Gen1 (TX Byte
Serializer and RX
Byte Deserializer
in X2 mode), Gen2
(TX Byte Serializer
and RX Byte
Deserializer in X2
mode)
Gen3
tx_parallel_data tx_
parallel_
data[7:0]
tx_parallel_
data[29:22,7:0
]
tx_parallel_
data[40:33,29:22,18:11,7:0]
UG-01143
2015.05.11
Native PHY IP Parameter Settings for PIPE
2-251
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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