User guide

Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE
Enable TX 8B/10B encoder Enabled Enabled Enabled
Enable TX 8B/10B disparity
control
Enabled Enabled Enabled
Enable RX 8B/10B decoder Enabled Enabled Enabled
Rate Match FIFO
Rate Match FIFO mode PIPE, PIPE 0ppm PIPE, PIPE 0ppm PIPE, PIPE 0ppm
RX rate match insert / delete -
ve pattern (hex)
0x0002f17c (K28.5/
K28.0/)
0x0002f17c (K28.5/
K28.0/)
0x0002f17c (K28.5/K28.0/)
RX rate match insert / delete
+ve pattern (hex)
0x000d0e83 (K28.5/
K28.0/)
0x000d0e83 (K28.5/
K28.0/)
0x000d0e83 (K28.5/K28.0/)
Enable rx_std_rmfifo_full
port
Optional Optional Optional
Enable rx_std_rmfifo_empty
port
Optional Optional Optional
PCI Express Gen 3 rate match
FIFO mode
Bypass Bypass 600
Word Aligner and Bit Slip
Enable TX bit slip Off Off Off
Enable tx_std_bitslipboun-
darysel port
Optional Optional Optional
RX word aligner mode
Synchronous State
Machine
Synchronous State
Machine
Synchronous State Machine
RX word aligner pattern length 10 10 10
RX word aligner pattern (hex)
0x0000 00000000017c
(/K28.5/)
0x0000 00000000017c
(/K28.5/)
0x0000 00000000017c(/
K28.5/)
Number of word alignment
patterns to achieve sync
3 3 3
Number of invalid data words
to lose sync
16 16 16
Number of valid data words to
decrement error count
15 15 15
Enable rx_std_wa_patterna-
lign port
Optional Optional Optional
Enable rx_std_wa_a1a2size
port
Off Off Off
Enable rx_std_bitslipboun-
darysel port
Optional Optional Optional
Enable rx_bitslip port Off Off Off
Bit Reversal and Polarity Inversion
2-250
Native PHY IP Parameter Settings for PIPE
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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