User guide

Gen1 PIPE Gen2 PIPE Gen3 PIPE
Enable rx_pma_qpipulldn
port (QPI)
Off Off Off
Enable rx_is_lockedtodata
port
Optional Optional Optional
Enable rx_is_lockedtoref
port
Optional Optional Optional
Enable rx_set_locktodata
and rx_set_locktoref ports
Optional Optional Optional
Enable rx_seriallpbken port Optional Optional Optional
Enable PRBS Verifier Control
and Status ports
Optional Optional Optional
Table 2-160: Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - Standard PCS
Parameter Gen1 PIPE Gen2 PIPE Gen3 PIPE
Standard PCS configurations
Standard PCS / PMA interface
width
10 10 10
(36)
FPGA Fabric / Standard TX
PCS interface width
8, 16 16 32
FPGA Fabric / Standard RX
PCS interface width
8, 16 16 32
Enable Standard PCS low
latency mode
Off Off Off
Standard PCS FIFO
TX FIFO mode low_latency low_latency low_latency
RX FIFO Mode low_latency low_latency low_latency
Enable tx_std_pcfifo_full
port
Optional Optional Optional
Enable tx_std_pcfifo_empty
port
Optional Optional Optional
Enable rx_std_pcfifo_full Optional Optional Optional
Enable rx_std_pcfifo_empty
port
Optional Optional Optional
Byte Serializer and Deserializer
TX byte serializer mode Disabled, Serialize x2 Serialize x2 Serialize x4
RX byte deserializer mode Disabled, Serialize x2 Serialize x2 Deserialize x4
8B/10B Encoder and Decoder
(36)
The PIPE is configured in Gen1/Gen2 during Power Up. Gen3 PCS is configured for PCS/PMA width of 32.
UG-01143
2015.05.11
Native PHY IP Parameter Settings for PIPE
2-249
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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