User guide

Gen1 PIPE Gen2 PIPE Gen3 PIPE
Initial TX PLL clock input selection
0 0
Gen1 / Gen2 clock
connection should be used
for Initial clock input
selection in Gen3x1
All other modes: 0
TX PMA Optional Ports
Enable tx_pma_clkout port Optional Optional Optional
Enable tx_pma_div_clkout port Optional Optional Optional
tx_pma_div_clkout division factor Optional Optional Optional
Enable tx_pma_elecidle port Off Off Off
Enable tx_pma_qpipullup port (QPI) Off Off Off
Enable tx_pma_qpipulldn port (QPI) Off Off Off
Enable tx_pma_txdetectrx port (QPI) Off Off Off
Enable tx_pma_rxfound port (QPI) Off Off Off
Enable rx_seriallpbken port Off Off Off
Table 2-159: Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes - RX PMA
Gen1 PIPE Gen2 PIPE Gen3 PIPE
RX CDR Options
Number of CDR reference
clocks
1 1 1
Selected CDR reference clock 0 0 0
Selected CDR reference clock
frequency
100, 125 MHz 100, 125 MHz 100, 125 MHz
PPM detector threshold 1000 1000 1000
Equalization
CTLE adaptation mode Manual / Triggered Manual / Triggered Manual / Triggered
DFE adaptation mode Disabled Disabled Disabled
Number of fixed dfe taps NA NA NA
RX PMA Optional Ports
Enable rx_pma_clkout port Optional Optional Optional
Enable rx_pma_div_clkout
port
Optional Optional Optional
rx_pma_div_clkout division
factor
Optional Optional Optional
Enable rx_pma_clkslip port Optional Optional Optional
2-248
Native PHY IP Parameter Settings for PIPE
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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