User guide

Figure 2-89: Connection Guidelines for a PIPE Gen3 Design
ATX PLL
and Master
CGB (Gen3)
fPLL
(Gen1/Gen2)
Arria 10
Transceiver
Native PHY
tx_bonding_clocks
tx_serial_clk
pll_pcie_clk
tx_bonding_clocks
pipe_hclk_in
Reset Controller
pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset
rx_cal_busy
rx_islockedtoref
clock reset tx_ready
rx_ready
pll_cal_busy pll_locked pll_locked
pll_cal_busy
pll_refclk
tx_cal_busy
mcgb_aux_clk
Related Information
• Arria 10 Standard PCS Architecture on page 5-37
• PLLs on page 3-3
For information about PLL architecture and implementation details.
• Resetting Transceiver Channels on page 4-1
For information about the Reset controller and implementation details.
• Using PLLs and Clock Networks on page 3-49
• Design Example on page 2-267
Native PHY IP Parameter Settings for PIPE
Table 2-157: Parameters for Arria 10 Native PHY IP in PIPE Gen1, Gen2, Gen3 Modes
Gen1 PIPE Gen2 PIPE Gen3 PIPE
Parameter
Message level for rule violations Error Error Error
Datapath Options
Transceiver configuration rules Gen1 PIPE Gen2 PIPE Gen3 PIPE
PMA configuration rules Basic Basic Basic
2-246
Native PHY IP Parameter Settings for PIPE
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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