User guide

Figure 2-86: Use ATX PLL or fPLL for Gen1/Gen2/Gen3 x1 Mode
CDR
CGB
Ch 4
CDR
CGB
Ch 3
CDR
CGB
Ch 2
CDR
CGB
Ch 1
CDR
CGB
Ch 0
CDR
CGB
Ch 5
4
4Master
CGB1
Master
CGB0
6
6
6
6
6
6
X1 Network
ATX PLL1
fPLL1
fPLL0
ATX PLL0
Notes:
1. The figure shown is just one possible combination for the PCIe Gen1/Gen2/Gen3 x1 mode.
2. Gen1/Gen2 modes use the fPLL only.
3. Gen3 mode uses the ATX PLL only.
4. Use the pll_pcie_clk from the fPLL, configured as Gen1/Gen2. This is the hclk required by the PIPE interface.
5. Select the number of TX PLLs (2) in the Native PHY wizard.
2-242
How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
Send Feedback