User guide

Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 2.0
Gen3 Features
The following subsections describes the Arria 10 transceiver block support for PIPE Gen3 features.
The PCS supports the PIPE 3.0 base specification. The 32-bit wide PIPE 3.0-based interface controls PHY
functions such as transmission of electrical idle, receiver detection, and speed negotiation and control.
Auto-Speed Negotiation
PIPE Gen3 mode enables ASN between Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and Gen3 (8.0 Gbps) signaling
data rates. The signaling rate switch is accomplished through frequency scaling and configuration of the
PMA and PCS blocks using a fixed 32-bit wide PIPE 3.0-based interface.
The PMA switches clocks between Gen1, Gen2, and Gen3 data rates. For a non bonded x1 channel, an
ASN module facilitates speed negotiation in that channel. For bonded x2, x4, and x8 channels, the ASN
module selects the master channel to control the rate switch. The master channel distributes the speed
change request to the other PMA and PCS channels.
The PCIe Gen3 speed negotiation process is initiated when Hard IP or the FPGA fabric requests a rate
change. The ASN then places the PCS in reset, and dynamically shuts down the clock paths to disengage
the current active state PCS (either Standard PCS or Gen3 PCS). If a switch to or from Gen3 is requested,
the ASN automatically selects the correct PCS clock paths and datapath selection in the multiplexers. The
ASN block then sends a request to the PMA block to switch the data rate, and waits for a rate change done
signal for confirmation. When the PMA completes the rate change and sends confirmation to the ASN
block, the ASN enables the clock paths to engage the new PCS block and releases the PCS reset. Assertion
of the pipe_phy_status signal by the ASN block indicates the successful completion of this process.
Note:
In Native PHY IP PIPE Core configuration, you must set pipe_rate[1:0]to initiate the
transceiver datarate switch sequence.
Rate Switch
This section provides an overview of auto rate change between PIPE Gen1 (2.5 Gbps), Gen2 (5.0 Gbps),
and Gen3 (8.0 Gbps) modes.
In Arria 10 devices, there is one ASN block common to the Standard PCS and Gen3 PCS, located in the
PMA PCS interface that handles all PIPE speed changes. The PIPE interface clock rate is adjusted to
match the data throughput when a rate switch is requested.
Table 2-156: PIPE Gen3 32 bit PCS Clock Rates
PCIe Gen3 Capability
Mode Enabled
Gen1 Gen2 Gen3
Lane data rate 2.5 Gbps 5 Gbps 8 Gbps
PCS clock frequency 250 MHz 500 MHz 250 MHz
FPGA Core IP clock
frequency
62.5 MHz 125 MHz 250 MHz
PIPE interface
width
32-bit 32-bit 32-bit
UG-01143
2015.05.11
Gen3 Features
2-235
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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