User guide

Figure 2-74: Rate Match Deletion
This figure shows an example of rate match deletion in the case where two /K28.0/ SKP symbols must be
deleted. Only one /K28.0/ SKP symbol is deleted per SKP ordered set received.
K28.5 K28.0 Dx.y K28.5 K28.0 K28.0 K28.0tx_parallel_data
First Skip Ordered Set Second Skip Ordered Set
Skip Symbol
Deleted
K28.5 Dx.y K28.5 K28.0 K28.0rx_parallel_data
pipe_rx_status[2:0]
3’b010 xxx 3’b010 xxx xxx
Figure 2-75: Rate Match Insertion
The figure below shows an example of rate match insertion in the case where two SKP symbols must be
inserted. Only one /K28.0/ SKP symbol is inserted per SKP ordered set received.
tx_parallel_data
rx_parallel_data
First Skip Ordered Set
Second Skip Ordered Set
Skip Symbol Inserted
K28.5 K28.0 Dx.y K28.5 K28.0 K28.0 K28.0 K28.0
K28.5 K28.0 K28.0 Dx.y K28.5 K28.0
K28.0 K28.0 K28.0 K28.0
pipe_rx_status[2:0]
3’b001 xxx xxx xxx 3’b001 xxx
xxx xxx xxx xxx
Figure 2-76: Rate Match FIFO Full
The rate match FIFO in PIPE mode automatically deletes the data byte that causes the FIFO to go full and
drives pipe_rx_status[2:0] = 3'b101 synchronous to the subsequent data byte. The figure below shows
the rate match FIFO full condition in PIPE mode. The rate match FIFO becomes full after receiving data
byte D4.
D1 D2 D3 D4 D5 D6 D7 D8
D1 D2 D3 D4 D8 xx xx xxD6
D7
tx_parallel_data
rx_parallel_data
pipe_rx_status[2:0] xxx xxx xxx xxx 3’b101 xxx xxx xxx
UG-01143
2015.05.11
Gen1 and Gen2 Clock Compensation
2-233
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
Send Feedback