User guide

Table 2-154: Supported Features for PIPE Configurations
Protocol Feature
Gen1
(2.5 Gbps)
Gen2
(5 Gbps)
Gen3
(8 Gbps)
x1, x2, x4, x8 link configurations Yes Yes Yes
PCIe-compliant synchronization state machine Yes Yes Yes
±300 ppm (total 600 ppm) clock rate compensation Yes Yes Yes
Transmitter driver electrical idle Yes Yes Yes
Receiver Detection Yes Yes Yes
8B/10B encoding/decoding disparity control Yes Yes No
128b/130b encoding/decoding No No Yes (supported
through the Gearbox)
Scrambling/Descrambling No No Yes (implemented in
FPGA fabric)
Power state management Yes Yes Yes
Receiver PIPE status encoding pipe_rxstatus[2:0] Yes Yes Yes
Dynamic switching between 2.5 Gbps and 5 Gbps
signaling rate
No Yes No
Dynamic switching between 2.5 Gbps, 5 Gbps, and 8
Gbps signaling rate
No No Yes
Dynamic transmitter margining for differential
output voltage control
No Yes Yes
Dynamic transmitter buffer de-emphasis of –3.5 dB
and –6 dB
No Yes Yes
Dynamic Gen3 transceiver pre-emphasis, de-
emphasis, and equalization
No No Yes
PCS PMA interface width (bits) 10 10 32
Receiver Electrical Idle Inference (EII) Implement in
FPGA fabric
Implement
in FPGA
fabric
Implement in FPGA
fabric
Related Information
PCIe Gen3 PCS Architecture
For more information about PIPE Gen3.
Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 2.0
Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express 3.0
Gen1/Gen2 Features
In a PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status
signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks. The PIPE
2-230
Gen1/Gen2 Features
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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