User guide

Transceiver Channel Datapath for PIPE
Figure 2-72: Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
PIPE Interface
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data rx_serial_data
FPGA
Fabric
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
PRBS
Verifier
PCI Express Hard IP
Figure 2-73: Transceiver Channel Datapath for PIPE Gen1/Gen2/Gen3 Configurations
RX
FIFO
Byte
Deserializer
8B/10B Decoder
Rate Match FIFO
Block
Synchronizer
Rate Match
FIFO
Gearbox
Receiver PMA
Word Aligner
Deserializer
CDR
Receiver Standard PCS
Receiver Gen3 PCS
Transmitter Gen3 PCS
rx_serial_data
PRBS
Verifier
PIPE Interface
FPGA
Fabric
Transmitter Standard PCS
Transmitter PMA
Serializer
tx_serial_data
TX
FIFO
Byte Serializer
8B/10B Encoder
PRBS
Generator
TX Bit Slip
PCI Exxpress Hard IP
Supported PIPE Features
PIPE Gen1, Gen2, and Gen3 configurations support different features.
UG-01143
2015.05.11
Transceiver Channel Datapath for PIPE
2-229
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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