User guide

Related Information
• PLLs and Clock Networks on page 3-1
• Transceiver Basics
Online training course for transceivers.
PHY Layer Transceiver Components
Transceivers in Arria 10 devices support both Physical Medium Attachment (PMA) and Physical Coding
Sublayer (PCS) functions at the physical (PHY) layer.
A PMA is the transceiver's electrical interface to the physical medium. The transceiver PMA consists of
standard blocks such as:
• serializer/deserializer (SERDES)
• clock and data recovery PLL
• analog front end transmit drivers
• analog front end receive buffers
The PCS can be bypassed with a PCS Direct configuration. Both the PMA and PCS blocks are fed by
multiple clock networks driven by high performance PLLs. In PCS Direct configuration, the data flow is
through the PCS block, but all the internal PCS blocks are bypassed. In this mode, the PCS functionality is
implemented in the FPGA fabric.
The GX Transceiver Channel
Figure 1-17: GX Transceiver Channel in Full Duplex Mode.
Standard PCS
PCIe Gen3 PCS
Enhanced PCSKR FEC
PCS Direct
HIP
(Optional)
Soft PIPE
(Optional)
FPGA Fabric
Transmitter PCS
Transmitter PMA
Serializer
Standard PCS
PCIe Gen3 PCS
Enhanced PCSKR FEC
PCS Direct
Receiver PCS
Receiver PMA
DeserializerCDR
Notes:
(1) The FPGA Fabric - PCS and PCS-PMA interface widths are configurable.
(1)
(1)
(1)
(1)
Arria 10 GX transceiver channels have three types of PCS blocks that together support continuous data
rates between 611 Mbps and 17.4 Gbps.
1-20
PHY Layer Transceiver Components
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Overview
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