User guide

PCI Express (PIPE)
You can use Arria 10 transceivers to implement a complete PCI Express solution for Gen1, Gen2, and
Gen3, at data rates of 2.5, 5.0, and 8 Gbps, respectively.
You can configure the transceivers for PCIe functionality using one of the following methods:
• Arria 10 Hard IP for PCIe
This is a complete PCIe solution that includes the Transaction, Data Link, and PHY/MAC layers. The
Hard IP solution contains dedicated hard logic, which connects to the transceiver PHY interface.
Note: For more information, refer to the Arria 10 Avalon-ST Interface for PCIe Solutions User Guide.
• Native PHY IP Core in PIPE Gen1/Gen2/Gen3 Transceiver Configuration Rules
You can use the Native PHY to configure the transceiver in PCIe mode, giving access to the PIPE
interface (commonly called PIPE mode in transceivers). This mode enables you to connect the
transceiver to a third-party MAC to create a complete PCIe solution.
The PIPE specification (version 3.0) provides implementation details for a PCIe-compliant physical
layer. The Native PHY IP Core for PIPE Gen1, Gen2, and Gen3 supports x1, x2, x4, or x8 operation for
a total aggregate bandwidth ranging from 2 to 64 Gbps. In a x1 configuration, the PCS and PMA
blocks of each channel are clocked and reset independently. The x2, x4, and x8 configurations support
channel bonding for two-lane, four-lane, and eight-lane links. In these bonded channel configurations,
the PCS and PMA blocks of all bonded channels share common clock and reset signals.
Gen1 and Gen2 modes use 8B/10B encoding, which has a 20% overhead to overall link bandwidth. Gen3
modes use 128b/130b encoding, which has an overhead of less than 2%. Gen1 and Gen2 modes use the
Standard PCS, and Gen3 mode uses the Gen3 PCS for its operation.
Table 2-153: Transceiver Solutions
Support Arria 10 Hard IP for PCI
Express
Native PHY IP Core for PCI Express (PIPE)
Gen1, Gen2, and Gen3 data rates Yes Yes
MAC, data link, and transaction layer Yes User implementation in FPGA core
Transceiver interface Hard IP through PIPE 3.0
based interface
• PIPE 2.0 for Gen1 and Gen2
• PIPE 3.0 based for Gen3 with
Gen1/Gen2 support
Related Information
Intel PHY Interface for the PCI Express (PIPE) Architecture PCI Express
Arria 10 Hard IP for PCI Express User Guide for the Avalon Streaming Interface
2-228
PCI Express (PIPE)
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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