User guide

Word Addr Bits R/W Register Name Description
0x066 [31:0] RO pma_rx_is_lockedtodata When asserted, indicates that the RX CDR
PLL is locked to the RX data, and that the
RX CDR has changed from LTR to LTD
mode. Bit <n> corresponds to channel <n>.
0x067 [31:0] RO pma_rx_is_lockedtoref When asserted, indicates that the RX CDR
PLL is locked to the reference clock. Bit <n>
corresponds to channel <n>.
XAUI PCS
0x084
[31:16] N/A Reserved N/A
[15:8]
R
Reserved N/A
[7:0] syncstatus[7:0]
Records the synchronization status of the
corresponding bit. The RX sync status
register has 1 bit per channel for a total of 4
bits per soft XAUI link; soft XAUI uses bits
0–3. Reading the value of the syncstatus
register clears the bits.
From block: Word aligner
0x085
[31:16] N/A Reserved N/A
[15:8]
R
errdetect[7:0]
When set, indicates that a received 10-bit
code group has an 8B/10B code violation or
disparity error. Use errdetect with
disperr to differentiate between a code
violation error, a disparity error, or both.
There are 2 bits per RX channel for a total of
8 bits per XAUI link. Reading the value of
the errdetect register clears the bits.
From block: 8B/10B decoder
[7:0] disperr[7:0]
Indicates that the received 10-bit code or
data group has a disparity error. When set,
the corresponding errdetect bits are also
set. There are 2 bits per RX channel for a
total of 8 bits per XAUI link. Reading the
value of the errdetect register clears the
bits.
From block: 8B/10B decoder
0x08a [0] RW simulation_flag Setting this bit to 1 shortens the duration of
reset and loss timer when simulating. Altera
recommends that you keep this bit set
during simulation.
2-226
XAUI PHY Register Interface and Register Descriptions
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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