User guide

Word Addr Bits R/W Register Name Description
0x042 [1:0]
W reset_control(write) Writing a 1 to bit 0 initiates a TX digital
reset using the reset controller module. The
reset affects channels enabled in the reset_
ch_bitmask. Writing a 1 to bit 1 initiates a
RX digital reset of channels enabled in the
reset_ch_bitmask. This bit self-clears.
R reset_status(read) Reading bit 0 returns the status of the reset
controller TX ready bit. Reading bit 1
returns the status of the reset controller RX
ready bit. This bit self-clears.
Reset Controls –Manual Mode
0x044
[31:4,0] RW Reserved It is safe to write 0s to reserved bits.
[1] RW reset_tx_digital Writing a 1 causes the internal TX digital
reset signal to be asserted, resetting all
channels enabled in reset_ch_bitmask.
You must write a 0 to clear the reset
condition.
[2] RW reset_rx_analog Writing a 1 causes the internal RX analog
reset signal to be asserted, resetting the RX
analog logic of all channels enabled in
reset_ch_bitmask. You must write a 0 to
clear the reset condition.
[3] RW reset_rx_digital Writing a 1 causes the RX digital reset signal
to be asserted, resetting the RX digital
channels enabled in reset_ch_bitmask.
You must write a 0 to clear the reset
condition.
PMA Control and Status Registers
0x061 [31:0] RW phy_serial_loopback Writing a 1 to channel <n> puts channel <n>
in serial loopback mode. For information
about pre- or post-CDR serial loopback
modes, refer to Loopback Modes.
0x064 [31:0] RW pma_rx_set_locktodata When set, programs the RX CDR PLL to
lock to the incoming data. Bit <n>
corresponds to channel <n>.
0x065 [31:0] RW pma_rx_set_locktoref When set, programs the RX CDR PLL to
lock to the reference clock. Bit <n>
corresponds to channel <n>.
UG-01143
2015.05.11
XAUI PHY Register Interface and Register Descriptions
2-225
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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