User guide

XAUI PHY Register Interface and Register Descriptions
The Avalon-MM PHY management interface provides access to the XAUI PHY IP core PCS, PMA, and
transceiver reconfiguration registers.
Table 2-150: Signals in the Avalon-MM PHY Management Interface
Signal Name Direction Description
phy_mgmt_clk Input
Avalon-MM clock input.
phy_mgmt_clk_reset Input Global reset signal that resets the entire XAUI PHY.
This signal is active high and level sensitive.
phy_mgmt_addr[8:0] Input 9-bit Avalon-MM address.
phy_mgmt_writedata[31:0] Input 32-bit input data.
phy_mgmt_readdata[31:0] Output 32-bit output data.
phy_mgmt_write Input Write signal. Asserted high.
phy_mgmt_read Input Read signal. Asserted high.
phy_mgmt_waitrequest Output When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write
request. When asserted, control signals to the
Avalon-MM slave interface must remain constant.
For more information about the Avalon-MM interface, including timing diagrams, refer to the Avalon
Interface Specification.
The following table specifies the registers that you can access using the Avalon-MM PHY management
interface using word addresses and a 32-bit embedded processor. A single address space provides access
to all registers.
Note:
Writing to reserved or undefined register addresses may have undefined side effects.
Table 2-151: XAUI PHY IP Core Registers
Word Addr Bits R/W Register Name Description
Reset Control Registers–Automatic Reset Controller
0x041 [31:0] RW reset_ch_bitmask
Bit mask for reset registers at addresses
0x042 and 0x044. The default value is all 1s.
You can reset channel <n> when bit<n> = 1.
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XAUI PHY Register Interface and Register Descriptions
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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