User guide

Signal Name Direction Description
xgmii_rx_inclk Input The XGMII SDR RX input clock which runs at 156.25
MHz. This port is only available when Enable phase
comensation FIFO is selected.
Transceiver Serial Data Interface
The XAUI transceiver serial data interface has four lanes of serial data for both the TX and RX interfaces.
This interface runs at 3.125 Gbps. There is no separate clock signal because it is encoded in the data.
Table 2-146: Serial Data Interface
Signal Name Direction Description
xaui_rx_serial_data[3:0] Input Serial input data.
xaui_tx_serial_data[3:0] Output Serial output data.
XAUI PHY Clocks, Reset, and Powerdown Interfaces
Figure 2-71: Clock Inputs and Outputs for IP Core with Soft PCS
XAUI Soft IP Core
4 x 3.125 Gbps serial
xgmii_rx_clk
xgmii_tx_clk
pll_ref_clk
phy_mgmt_clk
4
4
Soft PCS
pma_pll_inclk
pma_tx_clkout
tx_clkout
pma_rx_clkout
pll_ref_clk
sysclk
PMA
rx_recovered_clk
Table 2-147: Clock and Reset Signals
Signal Name Direction Description
pll_ref_clk Input This is a 156.25 MHz reference clock that is used by the
CDR logic.
XAUI PHY PMA Channel Controller Interface
Table 2-148: PMA Channel Controller Signals
Signal Name Direction Description
rx_recovered_clk[3:0] Output This is the RX clock, which is recovered from the received
data stream.
2-222
Transceiver Serial Data Interface
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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