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Figure 2-70: Interleaved SDR XGMII Data Mapping
Interleaved Result
Original XGMII Data
[63:56]
[55:48]
[47:40]
[39:32]
[31:24]
[23:16]
[15:8]
[7:0]
[63:56] [31:24] [55:48] [23:16] [47:40] [15:8] [39:32] [7:0]
Related Information
Avalon Interface Specifications
SDR XGMII TX Interface
Table 2-144: SDR TX XGMII Interface
Signal Name Direction Description
xgmii_tx_dc[71:0]
Input Contains 4 lanes of data and control for XGMII. Each lane
consists of 16 bits of data and 2 bits of control. Synchro‐
nous to mgmt_clk.
• Lane 0–[7:0]/[8], [43:36]/[44]
• Lane 1–[16:9]/[17], [52:45]/[53]
• Lane 2–[25:18]/[26], [61:54]/[62]
• Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_tx_clk
Input
The XGMII SDR TX clock which runs at 156.25 MHz.
SDR XGMII RX Interface
Table 2-145: SDR RX XGMII Interface
Signal Name Direction Description
xgmii_rx_dc_[71:0]
Output Contains 4 lanes of data and control for XGMII. Each lane
consists of 16 bits of data and 2 bits of control. Synchro‐
nous to mgmt_clk.
• Lane 0–[7:0]/[8], [43:36]/[44]
• Lane 1–[16:9]/[17], [52:45]/[53]
• Lane 2–[25:18]/[26], [61:54]/[62]
• Lane 3–[34:27]/[35],[70:63]/[71]
xgmii_rx_clk
Output
The XGMII SDR RX clock which runs at 156.25 MHz.
UG-01143
2015.05.11
SDR XGMII TX Interface
2-221
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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