User guide

Name Value Description
Enable dynamic reconfiguration On / Off When you turn this option on, you can connect
the dynamic reconfiguration ports to an external
reconfiguration module.
Enable rx_recovered_clk pin On / Off When you turn this option on, the RX recovered
clock signal is an output signal.
Enable phase compensation FIFO On / Off Enables the phase compensation FIFO to allow
different clocks on the xgmii interface.
XAUI PHY Ports
The following figure illustrates the top-level signals of the XAUI PHY IP core for the soft IP implementa‐
tion.
Figure 2-69: XAUI Top-Level Signals—Soft PCS and PMA
xgmii_tx_dc[71:0]
tx_bonding_clock[5:0]
xgmii_tx_clk
xmii_rx_dc[71:0]
xgmii_rx_clk
phy_mgmt_clk
phy_mgmt_clk_reset
phy_mgmt_address[8:0]
phy_mgmt_writedata[31:0]
phy_mgmt_readdata[31:0]
phy_mgmt_write
phy_mgmt_read
phy_mgmt_waitrequest
pll_ref_clk
pll_locked_i
pll_powerdown_o
cdr_ref_clk
XAUI Top-Level Signals
RX Status
Optional
xaui_rx_serial_data[3:0]
xaui_tx_serial_data[3:0]
rx_channelaligned
reconfig_clk
reconfig_reset
reconfig_write
reconfig_read
reconfig_waitrequest
rx_disperr[7:0]
reconfig_address[11:0]
reconfig_writedata[31:0]
reconfig_readdata[31:0]
rx_errdetect[7:0]
rx_syncstatus[7:0]
rx_recovered_clk[3:0]
rx_ready
tx_ready
Transceiver
Serial Data
SDR TX XGMII
SDR RX XGMII
Avalon-MM PHY
Avalon-MM
Management
Interface
Clocks
PLL
Dynamic
Reconfiguration
PMA
Channel
Controller
pll_cal_busy_i
xgmii_rx_inclk
XAUI PHY Interfaces
The XAUI PCS interface to the FPGA fabric uses a SDR XGMII interface. This interface implements a
simple version of the Avalon-ST protocol. The interface does not include ready or valid signals.
Consequently, the sources always drive data and the sinks must always be ready to receive data.
For more information about the Avalon-ST protocol, including timing diagrams, refer to the Avalon
Interface Specifications.
Depending on the parameters you choose, the application interface runs at either 156.25 Mbps or 312.5
Mbps. At either frequency, data is only driven on the rising edge of clock. To meet the bandwidth require‐
ments, the datapath is eight bytes wide with eight control bits, instead of the standard four bytes of data
and four bits of control. The XAUI PHY IP core treats the datapath as two, 32-bit data buses and includes
logic to interleave them, starting with the low-order bytes.
2-220
XAUI PHY Ports
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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