User guide

Note: When configuring ATX PLL, the PMA width setting must be set to 20-bit per transceiver channel.
This ensures that the serial clock is running at 3.125 Gbps while the input reference clock is 156.25
MHz.
Figure 2-68: Transceiver Clocking for XAUI Configuration With Phase Compensation FIFO Enabled
When phase compensation FIFO is enabled, you can connect the core to different clocks on the Avalon-
ST interface.
RX Phase
Compensation
FIFO
TX Phase
Compensation
FIFO
Receiver Standard PCS Receiver PMA
Deserializer
CDR
Transmitter Standard PCS
Transmitter PMA
Serializer
8B/10B
Decoder
Rate Match FIFO
Deskew FIFO
Word Aligner
8B/10B Encoder
Soft PCS
XAUI PHY IP Core
xgmii_tx_clk 156.25 MHz
Parallel Clock (x6 Network)
Serial Clock
ATX PLL
Idle Rep
Idle Converter
32/64b
Avalon-ST
Adapter
MAC
36/72b
XGMII
Adapter
Master CGB
x1 Network
fPLL
REFCLK 156.25 MHz
156.25 MHz 312.5 MHz 156.25 MHz
Parallel Recovered Clock 2 (1) Parallel Recovered Clock
Serial Recovered Clock
156.25 MHz
Serial Clock (x6 Network)
Parallel Clock (x6 Network)
Parallel Recovered Clock
Serial Recovered Clock
Parallel Recovered Clock 2
Parallel Clock
Note:
1. One recovered clock drives four XAUI channels.
XAUI PHY Performance and Resource Utilization
The following table lists the typical expected device resource utilization for different configurations using
the current version of the Quartus II software targeting an Arria 10 device. The numbers of combinational
ALUTs and logic registers are rounded to the nearest 100.
Table 2-141: XAUI PHY Performance and Resource Utilization
Implementation Number of 3.125
Gbps Channels
Combinational
ALUTs
Dedicated Logic
Registers
M20K Memory Blocks
Soft XAUI 4 1700 1700 3
Parameterizing the XAUI PHY
Complete the following steps to configure the XAUI PHY IP core in the IP Catalog:
2-218
XAUI PHY Performance and Resource Utilization
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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