User guide

Figure 2-66: Implementation of the XGMII Specification in Arria 10 Devices Configuration

Lane 0

Interface Clock (156.25 MHz)

8-bit

Interface Clock (156.25 MHz)

XGMII Transfer (DDR)

Lane 1

Lane 0

Lane 1

{D1, D0} {D3, D2}

Lane 2

Lane 3

{D1, D0} {D3, D2}

D1 D2 D3

D0 D1 D2 D3

Lane 2

Lane 3

D0 D1 D2 D3

16-bit

Arria 10 Soft PCS Interface (SDR)

8B/10B Encoding/Decoding

Each of the four lanes in a XAUI configuration supports an independent 8B/10B encoder/decoder as

specified in Clause 48 of the IEEE802.3-2008 specification. 8B/10B encoding limits the maximum number

of consecutive 1s and 0s in the serial data stream to five. This limit ensures DC balance as well as enough

transitions for the receiver CDR to maintain a lock to the incoming data.

The XAUI PHY IP core provides status signals to indicate both running disparity and the 8B/10B code

group error.

Transmitter and Receiver State Machines

In a XAUI configuration, the Arria 10 soft PCS implements the transmitter and receiver state diagrams

shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.

UG-01143

2015.05.11

XAUI Supported Features

2-215

Implementing Protocols in Arria 10 Transceivers

Altera Corporation

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