User guide

Figure 2-65: Transceiver Channel Datapath for XAUI Configuration
The XAUI configuration uses both the soft PCS and the Standard PCS as shown in the following figure.
RX Phase
Compensation
FIFO
TX Phase
Compensation
FIFO
Byte
Deserializer
Byte Serializer
Receiver Standard PCS Receiver PMA
Deserializer
CDR
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Transmitter Standard PCS
Portable solution using Custom PHY or Native PHY
Channel 0
Channel 1
Channel 2
Channel 3
Transmitter PMA Ch0
Transmitter PMA Ch1
Transmitter PMA Ch2
Transmitter PMA Ch3
Serializer
tx_serial_data
rx_serial_data
8B/10B
Decoder
Rate Match FIFO
Deskew FIFO
Word Aligner
8B/10B Encoder
16 20 20
2016
20 20 20
10
1010
Soft PCS
Soft PCS
Soft PCS
Soft PCS
FPGA Fabric
Channel 3
Channel 2
Channel 1
Channel 0
XAUI Supported Features
64-Bit SDR Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the XAUI PCS and
the Ethernet MAC/RS. Each of the four XAUI lanes must transfer 8-bit data and a 1-bit control code at
both the positive and negative edge (double data rate) of the 156.25 MHz interface clock.
Arria 10 transceivers and a soft PCS solution in a XAUI configuration do not support the XGMII
interface to the MAC/RS as defined in the IEEE 802.3-2008 specification. Instead, they transfer 16-bit data
and the 2-bit control code on each of the four XAUI lanes. The transfer occurs only at the positive edge
(single data rate) of the 156.25 MHz interface clock.
2-214
XAUI Supported Features
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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