User guide

Figure 2-64: XAUI PHY IP Core
XAUI PHY IP Core
4 x 3.125 Gbps serial
XAUI PHY IP
Hard PMA
PCS
8B/10B
Word Aligner
Phase Comp
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
Control & Status
4
4
Altera's third-party IP partner for Dual Data Rate XAUI (DDR XAUI or DXAUI) and Reduced XAUI
(RXAUI) support is MorethanIP (MTIP).
Related Information
• IEEE 802.3 Clause 48
• MorethanIP
Transceiver Datapath in a XAUI Configuration
The XAUI PHY IP core is partially implemented in soft logic inside the FPGA core. You must ensure that
your channel placement is compatible with the soft PCS implementation.
UG-01143
2015.05.11
Transceiver Datapath in a XAUI Configuration
2-213
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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