User guide

• ModelSim Verilog
• ModelSim VHDL
• VCS Verilog
• VCS VHDL
• NCSIM Verilog
• NCSIM VHDL simulation
When you generate a 1G/10GbE or 10GBASE-KR PHY IP core, the Quartus II software optionally
generates an IP functional simulation model.
TimeQuest Timing Constraints
To pass timing analysis, you must decouple the clocks in different time domains. The necessary Synopsys
Design Constraints File (.sdc) timing constraints are included in the top-level wrapper file.
XAUI PHY IP Core
In a XAUI configuration, the transceiver channel data path is configured using a soft PCS. The XAUI
configuration provides the transceiver channel datapath, clocking, and channel placement guidelines. You
can implement a XAUI link using the IP Catalog. Under Ethernet in the Interfaces menu, select the XAUI
PHY IP core. The XAUI PHY IP core implements the XAUI PCS in soft logic.
XAUI is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE
802.3ae-2008 specification. The XAUI PHY uses the XGMII interface to connect to the IEEE802.3 MAC
and Reconciliation Sublayer (RS). The IEEE 802.3ae-2008 specification requires the XAUI PHY link to
support:
• A 10 Gbps data rate at the XGMII interface
• Four lanes each at 3.125 Gbps at the PMD interface
UG-01143
2015.05.11
TimeQuest Timing Constraints
2-211
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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