User guide

default configuration includes two channels for backplane Ethernet and two channels for line-side (1G/
10G) applications.
Figure 2-62: 1G/10GbE PHY Only Design Example
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
1G/10GbE PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
XGMII
CLK FPLL
1G Ref CLK
CMU PLL
10G Ref CLK
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
CH0: PHY_ADDR = 0x0 nnn
CH1: PHY_ADDR = 0x1 nnn
CH2: PHY_ADDR = 0x2 nnn
CH3: PHY_ADDR = 0x3 nnn
NF_IP_WRAPPER
XGMII
Source
XGMII
Sink
XGMII
GEN
XGMII
CHK
...
Test Harness
XGMII
Source
XGMII
Sink
XGMII
GEN
XGMII
CHK
...
Test Harness
TH0_ADDR = 0xF nnn
TH1_ADDR = 0xE nnn
Management
Master
JTAG-to-
Avalon-MM
Master
ISSP
Clock and
Reset
NF_DE_WRAPPER
Related Information
Arria 10 Transceiver PHY Design Examples
Simulation Support
The 1G/10GbE and 10GBASE-KR PHY IP core supports the following Altera-supported simulators for
this Quartus II software release:
2-210
Simulation Support
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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