User guide

• ATX PLL on page 3-3
• Using the Altera Transceiver PHY Reset Controller on page 4-9
• 1G/10GbE PHY Functional Description on page 2-165
Design Guidelines
Consider the following guidelines while designing with 1G/10GbE PHY.
Using the 1G/10GbE PHY without the Sequencer
The sequencer brings up channel-based initial datapath and performs parallel detection. To use the 1G/
10GbE PHY without the sequencer, turn off the Enable automatic speed detection parameter.
Turning off the sequencer results in the following additional ports:
• rc_busy
• start_pcs_reconfig
• mode_1g_10gbar
These ports perform manual reconfiguration. The following figure shows how these ports are used for 1G
and 10G configuration.
Figure 2-61: Timing for Reconfiguration without the Sequencer
mgmt_clk
rc_busy
start_pcs_reconfig
mode_1g_10bar
Channel Placement Guidelines
The channels of multi-channel 1G/10G designs do not need to be placed contiguously. However, channels
instantiated in different transceiver banks require PLLs in the same bank.
Related Information
Arria 10 Avalon-MM Interface for PCIe Solutions
Design Example
Altera provides a design example to assist you in integrating your Ethernet PHY IP into your complete
design.
The MAC and PHY design example instantiates the 1G/10GbE PHY IP along with the 1G/10G Ethernet
MAC and supporting logic. It is part of the Quartus II software installation and is located in the
<quartus2_install_dir>/ip subdirectory. For more information about this example design, refer to the 10-
Gbps Ethernet MAC MegaCore Function User Guide.
A design example that instantiates the 1G/10G PHY and its supporting logic is available on the Altera
wiki. The following figure shows the block diagram of the 1G/10GbE PHY-only design example. The
UG-01143
2015.05.11
Design Guidelines
2-209
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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