User guide

Addr Bit Access Name Description
0x482
1 RO HI_BER High BER status. When set to 1, the PCS reports
a high BER. When set to 0, the PCS does not
report a high BER.
2 RO BLOCK_LOCK Block lock status. When set to 1, the PCS is
locked to received blocks. When set to 0, the
PCS is not locked to received blocks.
3 RO TX_FIFO_FULL When set to 1, the TX_FIFO is full.
4 RO RX_FIFO_FULL When set to 1, the RX_FIFO is full.
7 RO Rx_DATA_READY When set to 1, indicates the PHY is ready to
receive data.
Arria 10 GMII PCS Registers
Addr Bit R/W Name Description
0x490
9 RW RESTART_AUTO_ NEGOTIATION Set this bit to 1 to restart the Clause 37 auto-
negotiation (AN) sequence. For normal
operation, set this bit to the default 0 value.
This bit is self-clearing.
12 RW AUTO_NEGOTIATION_ ENABLE Set this bit to 1 to enable Clause 37 AN. The
default value is 1.
15 RW Reset Set this bit to 1 to generate a synchronous reset
pulse which resets all the PCS state machines,
comma detection function, and the 8B/10B
encoder and decoder. For normal operation,
set this bit to 0. This bit self clears.
0x491
2 R LINK_STATUS A value of 1 indicates that a valid link is
operating. A value of 0 indicates an invalid
link. If link synchronization is lost, this bit is 0.
3 R AUTO_NEGOTIATION_ ABILITY A value of 1 indicates that the PCS function
supports Clause 37 AN.
5 R AUTO_NEGOTIATION_ COMPLETE A value of 1 indicates the following status:
• The AN process is complete.
• The AN control registers are valid.
2-202
Arria 10 GMII PCS Registers
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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