User guide

Word
Addr
Bit R/W Name Description
0x4
D6
to
0x4
FF
Reserved for 40G KR Left empty for address compatibility with 40G MAC
+PHY KR solution.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 6-1
Hard Transceiver PHY Registers
Table 2-135: Hard Transceiver PHY Registers
Addr Bit Access Name Description
0x000-
0x3FF
[9:0] RW Access to HSSI
registers
All registers in the physical coding sub-layer (PCS)
and physical media attachment (PMA) that you can
dynamically reconfigure are in this address space.
Refer to the Arria 10 Dynamic Transceiver Reconfigu‐
ration chapter for further information.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 6-1
Enhanced PCS Registers
Table 2-136: Enhanced PCS Registers
Addr Bit Access Name Description
0x480 31:0 RW Indirect_addr Because the PHY implements a single channel,
this register must remain at the default value of
0 to specify logical channel 0.
0x481
2 RW RCLR_ERRBLK_CNT Error block counter clear register. When set to 1,
clears the RCLR_ERRBLK_CNT register. When set
to 0, normal operation continues.
3 RW RCLR_BER_COUNT BER counter clear register. When set to 1, clears
the RCLR_BER_COUNT register. When set to 0,
normal operation continues.
UG-01143
2015.05.11
Hard Transceiver PHY Registers
2-201
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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