User guide

Word
Addr
Bit R/W Name Description
0x4
D5
27:24 R RXEQ CTLE Setting Most recent ctle_rc setting sent to the reconfig bundle
during RX equalization.
29:28 R RXEQ CTLE Mode Most recent ctle_mode setting sent to the reconfig
bundle during RX equalization.
31:30 R RXEQ DFE Mode Most recent dfe_mode setting sent to the reconfig bundle
during RX equalization.
UG-01143
2015.05.11
Register Definitions
2-199
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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