User guide

Related Information
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• Arria 10 Avalon-MM DMA Interface for PCIe Datasheet
• Arria 10 Avalon-ST Interface with SR-IOV for PCIe Datasheet
Arria 10 SX Device Package Details
The following tables list package sizes, available transceiver channels, and PCI Express Hard IP blocks for
Arria 10 SX devices.
Table 1-5: Package Details for SX Devices with Transceivers and HIP Blocks Located on the Left Side
Periphery of the Device
Device U19
(7)
F27
(8)
F29
(9)
F34
(10)
F35
(10)
K F40
(11)
N F40
(11)
Transceiver Count, PCIe Hard IP Block Count
SX 016 6, 1 12, 1 12, 1
SX 022 6, 1 12, 1 12, 1
SX 027 12, 1 12, 1 24, 2 24, 2
SX 032 12, 1 12, 1 24, 2 24, 2
SX 048 12, 1 24, 2 36, 2
SX 057 24, 2 36, 2 36, 2 48, 2
SX 066 24, 2 36, 2 36, 2 48, 2
Transceiver PHY Architecture Overview
A link is defined as a single entity communication port. A link can have one or more transceiver channels.
A transceiver channel is synonymous with a transceiver lane.
For example, a 10GBASE-R link has one transceiver channel or lane with a data rate of 10.3125 Gbps. A
40GBASE-R link has four transceiver channels. Each transceiver channel operates at a lane data rate of
10.3125 Gbps. Four transceiver channels give a total collective link bandwidth of 41.25 Gbps (40 Gbps
before and after 64B/66B Physical Coding Sublayer (PCS) encoding and decoding).
Transceiver Bank Architecture
The transceiver bank is the fundamental unit that contains all the functional blocks related to the device's
high speed serial transceivers.
(7)
Package U19: 19mm x 19mm package; 484 pins.
(8)
Package F27: 27mm x 27mm package; 672 pins.
(9)
Package F29: 29mm x 29mm package; 780 pins.
(10)
Packages F34 and F35: 35 mm x 35 mm package size ; 1152 pins.
(11)
Package F40: 40 mm x 40 mm package size ; 1517 pins.
1-16
Arria 10 SX Device Package Details
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Overview
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