User guide

Word
Addr
Bit R/W Name Description
0x4
B1
0
R SEQ Link Ready When asserted, the sequencer indicates the link is ready.
1 R SEQ AN timeout When asserted, the sequencer has had an AN timeout.
This bit is latched and is reset when the sequencer
restarts AN.
2 R SEQ LT timeout When set, indicates that the sequencer has had a timeout.
13:8 R SEQ Reconfig
Mode[5:0]
Specifies the sequencer mode for PCS reconfiguration.
The following modes are defined:
• Bit 8, mode[0]: AN mode
• Bit 9, mode[1]: LT Mode
• Bit 10, mode[2]: 10G data mode
• Bit 11, mode[3]: GbE data mode
• Bit 12, mode[4]: Reserved for XAUI
• Bit13, mode[5]: 10G FEC mode
16 R KR FEC ability
170.0
When set to 1, indicates that the 10GBASE-KR PHY
supports FEC. Set as parameter SYNTH_FEC. For more
information, refer to Clause 45.2.1.84 of IEEE 802.3ap-
2007.
17 R KR FEC err ind
ability 170.0
When set to 1, indicates that the 10GBASE-KR PHY is
capable of reporting FEC decoding errors to the PCS. For
more information, refer to Clause 74.8.3 of IEEE 802.3ap-
2007.
0x4
B2
0:10 RW Reserved —
11 RWSC KR FEC TX Error
Insert
Writing a 1 inserts one error pulse into the TX FEC
depending on the transcoder and burst error settings.
31:15 RWSC Reserved —
0x4
B5
to
0x4
BF
Reserved for 40G KR Intentionally left empty for address compatibility with
40G MAC + PHY KR solutions.
UG-01143
2015.05.11
Register Definitions
2-185
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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