User guide

Signal Name Direction Clock Domain Description
rx_block_lock Output Synchronous to rx_
clkout
Asserted to indicate that the block synchronizer
has established synchronization.
rx_hi_ber Output Synchronous to rx_
clkout
Asserted by the BER monitor block to indicate a
Sync Header high bit error rate greater than 10
-4
.
rx_is_
lockedtodata
Output Asynchronous signal When asserted, indicates the RX channel is locked
to input data.
tx_cal_busy Output Synchronous to
mgmt_clk
When asserted, indicates that the TX channel is
being calibrated.
rx_cal_busy Output Synchronous to
mgmt_clk
When asserted, indicates that the RX channel is
being calibrated.
lcl_rf Input Synchronous to
xgmii_tx_clk
When asserted, indicates a Remote Fault (RF).The
MAC sends this fault signal to its link partner. Bit
D13 of the Auto Negotiation Advanced Remote
Fault register (0xC2) records this error.
rx_clkslip Input Asynchronous signal When asserted, indicates that the deserializer has
either skipped one serial bit or paused the serial
clock for one cycle to achieve word alignment. As
a result, the period of the parallel clock could be
extended by 1 unit interval (UI) during the clock
slip operation.
rx_data_ready Output Synchronous to rx_
clkout
When asserted, indicates that the MAC can begin
sending data to the PHY.
Dynamic Reconfiguration Interface
You can use the dynamic reconfiguration interface signals to dynamically change between 1G and 10G
data rates.
Table 2-132: Dynamic Reconfiguration Interface Signals
Signal Name Direction Clock Domain Description
rc_busy Output Synchronous to mgmt_
clk
When asserted, indicates that reconfiguration is in
progress. Synchronous to the mgmt_clk. This
signal is only exposed under the following
condition:
• Turn on Enable internal PCS reconfiguration
logic
start_pcs_
reconfig
Input Synchronous to mgmt_
clk
When asserted, initiates reconfiguration of the
PCS. Sampled with the mgmt_clk. This signal is
only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration
logic
UG-01143
2015.05.11
Dynamic Reconfiguration Interface
2-181
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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