User guide

Signal Name XGMII Signal Name Description
xgmii_rx_dc[8] xgmii_sdr_ctrl[0] Lane 0 control
xgmii_rx_dc[16:9] xgmii_sdr_data[15:8] Lane 1 data
xgmii_rx_dc[17] xgmii_sdr_ctrl[1] Lane 1 control
xgmii_rx_dc[25:18] xgmii_sdr_data[23:16] Lane 2 data
xgmii_rx_dc[26] xgmii_sdr_ctrl[2] Lane 2 control
xgmii_rx_dc[34:27] xgmii_sdr_data[31:24] Lane 3 data
xgmii_rx_dc[35] xgmii_sdr_ctrl[3] Lane 3 control
xgmii_rx_dc[43:36] xgmii_sdr_data[39:32] Lane 4 data
xgmii_rx_dc[44] xgmii_sdr_ctrl[4] Lane 4 control
xgmii_rx_dc[52:45] xgmii_sdr_data[47:40] Lane 5 data
xgmii_rx_dc[53] xgmii_sdr_ctrl[5] Lane 5 control
xgmii_rx_dc[61:54] xgmii_sdr_data[55:48] Lane 6 data
xgmii_rx_dc[62] xgmii_sdr_ctrl[6] Lane 6 control
xgmii_rx_dc[70:63] xgmii_sdr_data[63:56] Lane 7 data
xgmii_rx_dc[71] xgmii_sdr_ctrl[7] Lane 7 control
GMII Interface
The GMII interface signals drive data to and from the PHY.
Table 2-129: GMII Interface Ports
Signal Name Direction Description
gmii_tx_d[7:0] Input Data to be encoded and sent to the link
partner. This signal is clocked with tx_pma_
clkout.
gmii_tx_en Input The GMII TX control signal. Synchronous
to mgmt_clk.
gmii_tx_err Input The GMII TX error signal. Synchronous to
mgmt_clk.
gmii_rx_d[7:0] Output Data to be encoded and sent to the link
partner. This signal is clocked with tx_pma_
clkout.
gmii_rx_dv Output The GMII RX control signal. Synchronous
to mgmt_clk.
gmii_rx_err Output The GMII RX error signal. Synchronous to
mgmt_clk.
UG-01143
2015.05.11
GMII Interface
2-179
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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