User guide

Signal Name Direction Description
rx_analogreset Input Resets the analog RX portion of the transceiver
PHY. Synchronous to mgmt_clk.
rx_digitalreset Input Resets the digital RX portion of the transceiver
PHY. Synchronous to mgmt_clk.
usr_seq_reset Input Resets the sequencer. Initiates a PCS reconfigura‐
tion, and may restart AN, LT or both if these modes
are enabled. Synchronous to mgmt_clk.
Related Information
• Input Reference Clock Sources on page 3-27
• PLLs on page 3-3
Data Interfaces
Table 2-126: XGMII Signals
The MAC drives the TX XGMII signals to the 10GbE PHY. The 10GbE PHY drives the RX XGMII signals to the
MAC.
Signal Name Direction Clock Domain Description
10GbE XGMII Data Interface
xgmii_tx_
dc[71:0]
Input
Synchronous to
xgmii_tx_clk
XGMII data and control for 8 lanes. Each lane
consists of 8 bits of data and 1 bit of control.
xgmii_tx_clk
Input
Clock signal
Clock for single data rate (SDR) XGMII TX interface
to the MAC. It should connect to xgmii_rx_clk. This
clock can be connected to the tx_div_clkout;
however, Altera recommends that you connect it to a
PLL for use with the Triple Speed Ethernet MegaCore
function. The frequency is 125 MHz for 1G and
156.25 MHz for 10G. This clock is driven from the
MAC.
The frequencies are the same whether or not you
enable FEC.
xgmii_rx_
dc[71:0]
Output
Synchronous to
xgmii_rx_clk
RX XGMII data and control for 8 lanes. Each lane
consists of 8 bits of data and 1 bit of control.
UG-01143
2015.05.11
Data Interfaces
2-177
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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