User guide

Parameter Name Options Description
Enable additional control and
status pins
On
Off
When you turn on this parameter, the core
includes the rx_block_lock and rx_hi_ber
ports.
Table 2-122: FEC Options
Parameter Name Options Description
Include FEC sublayer On
Off
When you turn on this parameter, the core
includes logic to implement FEC and a soft
10GBASE-R PCS.
10M/100M/1Gb Ethernet Parameters
The 10M/100M/1GbE parameters allow you to specify options for the MII interface and the 1GbE data
rate.
Table 2-123: 10M/100M/1Gb Ethernet
Parameter Name Options Description
Enable 1Gb Ethernet protocol On
Off
When you turn this option on, the core includes
the GMII interface and related logic.
Enable 10M/100Mb Ethernet
functionality
On
Off
When you turn this option on, the core includes
the MII PCS. It also supports 4-speed mode to
implement a 10M/100M interface to the MAC
for the GbE line rate.
PHY ID (32 bits) 32-bit value
An optional 32-bit value that serves as a unique
identifier for a particular type of PCS. The
identifier includes the following components:
• Bits 3-24 of the Organizationally Unique
Identifier (OUI) assigned by the IEEE
• 6-bit model number
• 4-bit revision number
If unused, do not change the default value which
is 0x00000000.
PHY Core version (16 bits) 16-bit value This is an optional 16-bit value that identifies the
PHY core version.
Speed Detection Parameters
Selecting the speed detection option gives the PHY the ability to detect to link partners that support 1G/
10GbE but have disabled Auto-Negotiation. During Auto-Negotiation, if AN cannot detect Differential
Manchester Encoding (DME) pages from a link partner, the Sequencer reconfigures to 1GE and 10GE
modes (Speed/Parallel detection) until it detects a valid 1G or 10GbE pattern.
UG-01143
2015.05.11
10M/100M/1Gb Ethernet Parameters
2-173
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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