User guide

Related Information
• General Options on page 2-129
• 10GBASE-R Parameters on page 2-130
• 10M/100M/1Gb Ethernet Parameters on page 2-173
• Speed Detection Parameters on page 2-173
• PHY Analog Parameters on page 2-174
General Options
The General Options allow you to specify options common to 10GBASE-KR mode.
Table 2-120: General Options Parameters
Parameter Name Options Description
Enable internal PCS reconfigura‐
tion logic
On
Off
This parameter is only an option when SYNTH_
SEQ = 0. When set to 0, it does not include the
reconfiguration module or expose the start_
pcs_reconfig or rc_busy ports. When set to 1,
it provides a simple interface to initiate reconfi‐
guration between 1G and 10G modes.
Enable IEEE 1588 Precision Time
Protocol
On
Off
When you turn on this parameter, you enable
the IEEE 1588 Precision Time Protocol logic for
both 1G and 10G modes.
Enable M20K block ECC
protection
On
Off
When you turn on this parameter, you enable
error correction code (ECC) support on the
embedded Nios CPU system. This parameter is
only valid for the backplane variant.
Enable tx_pma_clkout port On
Off
When you turn on this parameter, the tx_pma_
clkout port is enabled. Refer to the clock and
reset signals section for more information about
this port.
Enable rx_pma_clkout port On
Off
When you turn on this parameter, the rx_pma_
clkout port is enabled. Refer to the clock and
reset signals section for more information about
this port.
Enable tx_divclk port On
Off
When you turn on this parameter, the tx_
divclk port is enabled. Refer to the clock and
reset signals section for more information about
this port.
Enable rx_divclk port On
Off
When you turn on this parameter, the rx_
divclk port is enabled. Refer to the clock and
reset signals section for more information about
this port.
UG-01143
2015.05.11
General Options
2-171
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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