User guide

Signal Name Direction Description
rx_div_clk Output This is the receive div33 clock, which is recovered
from the received data. It drives the Auto Negotia‐
tion (AN) and Link Training (LT) logic and is
sourced from the Native PHY rx_pma_div_clkout
port. Note: Use tx_clkout or xgmii_rx_clk for
10G TX datapath clocking. If the PHY is reconfig‐
ured to 1G mode, the frequency will change. Its
frequency is 125, 156.25, or 312.5 MHz.
calc_clk_1g Input This is the clock for the GIGE PCS 1588 mode.
tx_analogreset Input Resets the analog TX portion of the transceiver
PHY. Synchronous to mgmt_clk.
tx_digitalreset Input Resets the digital TX portion of the transceiver
PHY. Synchronous to mgmt_clk.
rx_analogreset Input Resets the analog RX portion of the transceiver
PHY. Synchronous to mgmt_clk.
rx_digitalreset Input Resets the digital RX portion of the transceiver
PHY. Synchronous to mgmt_clk.
usr_seq_reset Input Resets the sequencer. Initiates a PCS reconfigura‐
tion, and may restart AN, LT or both if these modes
are enabled. Synchronous to mgmt_clk.
rx_data_ready Output When asserted, indicates that you can start to send
the 10G data. Synchronous to mgmt_clk.
Related Information
• Input Reference Clock Sources on page 3-27
• PLLs on page 3-3
Parameterizing the 1G/10GbE PHY
The Arria 10 1G/10GbE and 10GBASE-KR PHY IP core allows you to select either the Backplane-KR or
1Gb/10Gb Ethernet variant. The 1Gb/10Gb Ethernet variant (1G/10GbE) does not implement the link
training and auto-negotiation functions.
Complete the following steps to parameterize the 1Gb/10Gb Ethernet PHY IP core in the parameter
editor:
1. Instantiate the Arria 10 1G/10GbE and 10GBASE-KR PHY from the IP Catalog.
Refer to Select and Instantiate the PHY IP Core on page 2-2.
2. Select 1Gb/10Gb Ethernet from the IP variant list located under Ethernet MegaCore Type.
3. Use the parameter values in the tables in 10GBASE-R Parameters on page 2-130, 10M/100M/1Gb
Ethernet Parameters on page 2-173 , Speed Detection Parameters on page 2-173, and PHY Analog
Parameters on page 2-174 as a starting point. Or, you can select the BackPlane_wo_1588 option in
the Presets tab on the right side of the IP Parameter Editor. You can then modify the setting to meet
your specific requirements.
4. Click Generate HDL to generate the 1Gb/10Gb Ethernet IP core top-level HDL file.
2-170
Parameterizing the 1G/10GbE PHY
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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