User guide

Signal Name Direction Description
rx_cdr_refclk_1g Input The RX 1G PLL reference clock to drive the RX
HSSI circuits. Connected to the rx_cdr_refclk[1]
input of the native PHY.
mgmt_clk Input Avalon-MM clock and control system clock. Its
frequency range is 100 MHz to 125 MHz.
mgmt_clk_reset Input When asserted, it resets the whole PHY.
xgmii_tx_clk Input Clock for XGMII TX interface with MAC. Can be
connected to tx_div_clkout. This drives the tx_
coreclkin port of the Native PHY.
xgmii_rx_clk Input The clock for the XGMII RX interface with the
MAC. Altera recommends connecting it directly to
a PLL for use with TSE. This drives rx_coreclkin
of the native PHY. Its frequency is 156.25 or 312.5
MHz.
tx_clkout Output Transmit parallel clock. It is sourced from out_pld_
pcs_tx_clk_out on the HSSI. This could be used to
provide the XGMII clocks or the GMII clocks,
though if the PHY is reconfigured, the frequency
will change. Its frequency is 125, 156.25, 161, 258, or
312.5 MHz.
rx_clkout Output Receive parallel clock. It is sourced from out_pld_
pcs_rx_clk_out on the HSSI. If the PHY is
reconfigured, the frequency will change. Its
frequency is 125, 156.25, 161, 258, or 312.5 MHz.
tx_pma_clkout Output Transmit PMA clock. This is the clock for the 1588
mode TX FIFO and the 1G TX and RX PCS parallel
data interface. Note: Use tx_div_clkout or xgmii_
tx_clk for 10G TX datapath clocking. This clock is
provided for the 1G mode GMII/MII data and
SyncE mode where the clock can be used as a
reference to lock an external clock source. Its
frequency is 125, 161, or 258 MHz.
rx_pma_clkout Output Receive PMA clock. This is the clock for the 1588
mode RX FIFO and the 1G RX FIFO. Note: Use tx_
div_clkout or xgmii_rx_clk for 10G RX datapath
clocking. This clock is provided for the SyncE mode
where the clock can be used as a reference to lock an
external clock source. Its frequency is 125, 161, or
258 MHz.
tx_div_clk Output This is the transmit div33 clock, which is sourced
from the Native PHY tx_pma_div_clkout. It could
be connected to the xgmii_tx_clk and xgmii_rx_
clk clock inputs to drive the MAC interface, though
if the PHY is reconfigured to 1G mode, the
frequency will change. Its frequency is 125, 156.25,
or 312.5 MHz.
UG-01143
2015.05.11
Clock and Reset Interfaces
2-169
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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