User guide

Contents
Arria 10 Transceiver PHY Overview ..................................................................1-1
Device Transceiver Layout......................................................................................................................... 1-3
Arria 10 GX Device Transceiver Layout.......................................................................................1-3
Arria 10 GT Device Transceiver Layout.......................................................................................1-9
Arria 10 GX and GT Device Package Details ............................................................................1-12
Arria 10 SX Device Transceiver Layout......................................................................................1-13
Arria 10 SX Device Package Details............................................................................................ 1-16
Transceiver PHY Architecture Overview...............................................................................................1-16
Transceiver Bank Architecture.................................................................................................... 1-16
PHY Layer Transceiver Components......................................................................................... 1-20
Transceiver Phase-Locked Loops................................................................................................ 1-23
Clock Generation Block (CGB)................................................................................................... 1-24
Calibration..................................................................................................................................................1-24
Implementing Protocols in Arria 10 Transceivers.............................................2-1
Transceiver Design IP Blocks.....................................................................................................................2-1
Transceiver Design Flow.............................................................................................................................2-2
Select and Instantiate the PHY IP Core........................................................................................2-2
Configure the PHY IP Core............................................................................................................2-4
Generate the PHY IP Core..............................................................................................................2-5
Select the PLL IP Core.....................................................................................................................2-5
Configure the PLL IP Core.............................................................................................................2-7
Generate the PLL IP Core ..............................................................................................................2-8
Reset Controller ...............................................................................................................................2-8
Create Reconfiguration Logic.........................................................................................................2-8
Connect the PHY IP to the PLL IP and Reset Controller...........................................................2-9
Connect Datapath ...........................................................................................................................2-9
Make Analog Parameter Settings ..................................................................................................2-9
Compile the Design......................................................................................................................... 2-9
Verify Design Functionality......................................................................................................... 2-10
Arria 10 Transceiver Protocols and PHY IP Support...........................................................................2-10
Using the Arria 10 Transceiver Native PHY IP Core...........................................................................2-17
Presets..............................................................................................................................................2-19
General and Datapath Parameters ..............................................................................................2-19
PMA Parameters............................................................................................................................2-23
Enhanced PCS Parameters .......................................................................................................... 2-29
Standard PCS Parameters.............................................................................................................2-39
PCS Direct ......................................................................................................................................2-46
Dynamic Reconfiguration Parameters........................................................................................2-46
PMA Ports.......................................................................................................................................2-49
Enhanced PCS Ports......................................................................................................................2-54
Standard PCS Ports........................................................................................................................2-68
TOC-2
Arria 10 Transceiver PHY Overview
Altera Corporation