User guide

information in the MAC as part of the Precision Time Protocol implementation, refer to the 10-Gbps
Ethernet MAC MegaCore Function User Guide.
Reconfiguration Block
The reconfiguration logic performs the Avalon-MM writes to the PHY for both PCS and PMA reconfigu‐
ration. The following figure shows the details of the reconfiguration blocks. The Avalon-MM master
accepts requests from the PMA or PCS controller. It performs the Read-Modify-Write or Write
commands using the Avalon-MM interface. The PCS controller receives data rate change requests from
the Sequencer and translates them to a series of Read-Modify-Write or Write commands to the PMA and
PCS.
Figure 2-58: Reconfiguration Block Details
The 1G/10GbE PHY IP core is very flexible. For example, you can configure it with or without IEEE
1588v2, and with or without FEC in the enhanced PCS datapath.
PCS
Controller
TX EQ Controller
DFE Controller
CTLE Controller
PMA Controller
rcfg_data
rcfg_data
rcfg_data
(1)
rcfg_data
Avalon-MM
Decoder
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM Bus
Avalon-MM reconfig_busy Signal
HSSI
Reconfiguration
Requests
MGMT_CLK
(2)
PCS
Reconfiguration
Interface
PMA
Reconfiguration
Interface
Notes:
1. rcfg = Reconfiguration
2. MGMT_CLK = Management Clock
Related Information
• Arria 10 Enhanced PCS Architecture on page 5-18
• Arria 10 Standard PCS Architecture on page 5-37
• Arria 10 PMA Architecture on page 5-1
• 10-Gbps Ethernet MAC MegaCore Function User Guide.
For more information about latency in the MAC as part of the Precision Time Protocol implementa‐
tion.
Clock and Reset Interfaces
UG-01143
2015.05.11
Clock and Reset Interfaces
2-167
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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