User guide

Figure 2-57: 1G/10GbE PHY Block Diagram
Sequencer
(Auto-Speed
Detect)
Registers
Block
Reconfiguration
GigE
PCS
1588
FIFO
Auto-Negotiation
Clause 73
Link Training
Clause 72
HSSI Reconfiguration Requests
1588
FIFO
GigE
PCS
Native PHY
TX PMA
RX PMA
40/32
40/32
rx_pld_clk rx_pma_clk
tx_pld_clk tx_pma_clk
tx_pld_clk tx_pma_clk
rx_pld_clk rx_pma_clk
Divide by 33/1/2
Avalon-MM
User PCS Reconfiguration
MGMT_CLK
8 + 2
64 + 8
TX_GMII_DATA
XGMII_TX_CLK
TX_XGMII_DATA
TX_PMA_CLKOUT
RX_XGMII_DATA
64 + 8
8 + 2
XGMII_RX_CLK
RX_GMII_DATA
RX_PMA_CLKOUT
RX_DIV_CLKOUT
40
40
66
PMA Reconfiguration I/F
PCS Reconfiguration I/F
Soft Logic Hard Logic Not Available
Standard RX PCS
Standard TX PCS
Enhanced TX PCS
Enhanced RX PCS
Standard and Enhanced PCS Datapaths
The Standard PCS and PMA inside the Native PHY are configured as the Gigabit Ethernet PHY. The
Enhanced PCS and PMA inside the Native PHY are configured as the 10GBASE-R PHY. Refer to the
Standard PCS and Enhanced PCS architecture chapters for more details.
Sequencer
The Sequencer controls the start-up sequence of the PHY IP, including reset and power-on. It selects
which PCS (1G or 10G) and PMA interface is active. The Sequencer interfaces to the reconfiguration
block to request a change from one data rate to the other data rate.
GigE PCS
The GigE PCS includes the GMII interface and Clause 37 auto negotiation and SGMII functionality.
Soft Enhanced PCS FIFO for IEEE 1588v2
In IEEE 1588v2 mode, the enhanced PCS FIFOs for both TX and RX are constructed in soft IP to include
the latency information via the latency adjustment ports. For more information about the required latency
2-166
1G/10GbE PHY Functional Description
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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