User guide

Figure 2-56: Top Level Modules of the 1G/10GbE PHY MegaCore Function
The Enhanced PCS receives and transmits XGMII data. The Standard PCS receives and transmits GMII
data.
Altera Device with 10.3125-Gbps Transceivers
1G/10Gb Ethernet PHY MegaCore Function
Native PHY Hard IP
257.8 MHz
161.1 MHz
TX
Serial
Data
RX
Serial
Data
1 Gb SFP /
10 Gb SFP+
or XFP /
1G/10 Gb SFP+
Module/
Standard PHY
Product
1G/ 10 Gb
Ethernet
Network
Interface
322.265625 MHz
or 644.53125 MHz
Reference Clock
125 MHz
Reference Clock
Legend
Hard IP
Soft IP
ATX/CMU
TX PLL
For
10 GbE
CMU
or fPLL
TX PLL
For 1 GbE
1.25 Gb/
10.3125 Gb
Hard PMA
Link
Status
Sequencer
(Optional)
10 Gb
Ethernet
Enhanced PCS
w FEC
1 Gb
Ethernet
Standard
PCS
To/From Modules in the PHY MegaCore
Control and Status
Registers
Avalon-MM
PHY Management
Interface
PCS Reconfig
Request
Optional
1588 TX and
RX Latency
Adjust 1G
and 10G
To/From
1G/10Gb
Ethernet
MAC
RX GMII Data
TX GMII/MII Data
@ 125 MHz
RX XGMII Data
TX XGMII Data
@156.25 MHz
1 GigE
PCS
Reconfiguration
Block
40 64
40 64
Red = With FEC Option
An Avalon-MM slave interface provides access to the 1G/10GbE PHY IP Core registers. These registers
control many of the functions of the other blocks. Many of these bits are defined in Clause 45 of IEEE
802.3ap-2008 Standard.
Related Information
• IEEE Std 802.3ap-2008 Standard
• Standard for a Precision Clock Synchronization Protocol for Networked Measurement and
Control Systems
1G/10GbE PHY Release Information
This topic provides information about this release of the 1G/10GbE PHY IP Core.
Table 2-117: 1G/10GbE Release Information
Item Description
Version 15.0
2-164
1G/10GbE PHY Release Information
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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