User guide

Related Information
• fPLL on page 3-13
• CMU PLL on page 3-21
• ATX PLL on page 3-3
• Using the Altera Transceiver PHY Reset Controller on page 4-9
• 10GBASE-KR Functional Description on page 2-126
Design Example
Figure 2-55: PHY-Only Design Example with Two Backplane Ethernet and Two Line-Side (1G/10G)
Ethernet Channels
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
1588 Soft
FIFOs
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
Native Hard PHY
STD
RX PCS
TX PMA
RX PMA
STD
TX PCS
10-GB
TX PCS
10-GB
RX PCS
Divide
GMII
RS
Auto Neg
cls 73
Link Training
cls 72
KR PHY IP
Sequencer
NF
Reconfiguration
Registers CSR
Avalon-MM Slave
XGMII
CLK FPLL
1G Ref CLK
CMU PLL
10G Ref CLK
ATX PLL
Reset
Control
Reset
Control
Reset
Control
Reset
Control
CH0: PHY_ADDR = 0x0
CH1: PHY_ADDR = 0x1
CH2: PHY_ADDR = 0x2
CH3: PHY_ADDR = 0x3
NF_IP_WRAPPER
XGMII
Source
XGMII
Sink
XGMII
GEN
XGMII
CHK
...
Test Harness
XGMII
Source
XGMII
Sink
XGMII
GEN
XGMII
CHK
...
Test Harness
TH0_ADDR = 0xF nnn
TH1_ADDR = 0xE nnn
Management
Master
JTAG-to-
Avalon-MM
Master
ISSP
Clock and
Reset
NF_DE_WRAPPER
2-162
Design Example
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
Send Feedback