User guide

Word Addr Bit R/W Name Description
0x4D6 to
0x4FF
Reserved for 40G KR Left empty for address compatibility with 40G
MAC+PHY KR solution.
Hard Transceiver PHY Registers
Table 2-114: Hard Transceiver PHY Registers
Addr Bit Access Name Description
0x000-
0x3FF
[9:0] RW Access to HSSI
registers
All registers in the physical coding sub-layer (PCS)
and physical media attachment (PMA) that you can
dynamically reconfigure are in this address space.
Refer to the Arria 10 Dynamic Transceiver Reconfigu‐
ration chapter for further information.
Related Information
Reconfiguration Interface and Dynamic Reconfiguration on page 6-1
Enhanced PCS Registers
Table 2-115: Enhanced PCS Registers
Addr Bit Access Name Description
0x480 31:0 RW Indirect_addr Because the PHY implements a single channel,
this register must remain at the default value of
0 to specify logical channel 0.
0x481
2 RW RCLR_ERRBLK_CNT Error block counter clear register. When set to 1,
clears the RCLR_ERRBLK_CNT register. When set
to 0, normal operation continues.
3 RW RCLR_BER_COUNT BER counter clear register. When set to 1, clears
the RCLR_BER_COUNT register. When set to 0,
normal operation continues.
0x482
1 RO HI_BER High BER status. When set to 1, the PCS reports
a high BER. When set to 0, the PCS does not
report a high BER.
2 RO BLOCK_LOCK Block lock status. When set to 1, the PCS is
locked to received blocks. When set to 0, the
PCS is not locked to received blocks.
3 RO TX_FIFO_FULL When set to 1, the TX_FIFO is full.
4 RO RX_FIFO_FULL When set to 1, the RX_FIFO is full.
7 RO Rx_DATA_READY When set to 1, indicates the PHY is ready to
receive data.
PMA Registers
The PMA registers allow you to reset the PMA, customize the TX and RX serial data interface, and
provide status information.
2-160
Hard Transceiver PHY Registers
UG-01143
2015.05.11
Altera Corporation
Implementing Protocols in Arria 10 Transceivers
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