User guide

Word Addr Bit R/W Name Description

0x4D0

RW Link Training

enable

When 1, enables the 10GBASE-KR start-up

protocol. When 0, disables the 10GBASE-KR start-

up protocol. The default value is 1. For more

information, refer to Clause 72.6.10.3.1 and

10GBASE-KR PMD control register bit (1.150.1) of

IEEE 802.3ap

2007.

1 RW dis_max_wait_tmr When set to 1, disables the LT max_wait_timer.

Used for characterization mode when setting much

longer BER timer values.

2 RW quick_mode When set to 1, only the init and preset values are

used to calculate the best BER.

3 RW pass_one When set to 1, the BER algorithm considers more

than the first local minimum when searching for

the lowest BER. The default value is 1.

7:4 RW main_step_cnt [3:0] Specifies the number of equalization steps for each

main tap update. There are about 20 settings for

the internal algorithm to test. The valid range is 1-

15. The default value is 4'b0001.

11:8 RW prpo_step_cnt [3:0] Specifies the number of equalization steps for each

pre- and post-tap update. From 16-31 steps are

possible. The default value is 4'b0001.

UG-01143

2015.05.11

10GBASE-KR PHY Register Definitions

2-149

Implementing Protocols in Arria 10 Transceivers

Altera Corporation

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