User guide

In GT devices that have transceivers on both sides of the device, the GX transceiver channels on the right
side can be used in reduced power mode. In GT devices where none of the GT channels are used, the
transceiver channels can be used as GX channels in standard or reduced power mode.
Related Information
• Arria 10 GT Channel Usage on page 2-313
For details about Arria 10 GT channel usage guidelines
• Arria 10 Avalon-ST Interface for PCIe Datasheet
• Arria 10 Avalon-MM Interface for PCIe Datasheet
• Arria 10 Avalon-MM DMA Interface for PCIe Datasheet
• Arria 10 Avalon-ST Interface with SR-IOV for PCIe Datasheet
Arria 10 GX and GT Device Package Details
The following tables list package sizes, available transceiver channels, and PCI Express Hard IP blocks for
Arria 10 GX and GT devices.
Table 1-3: Package Details for GX and GT Devices with Transceivers and HIP Blocks Located on the Left
Side Periphery of the Device
• Package U19: 19mm x 19mm package; 484 pins.
• Package F27: 27mm x 27mm package; 672 pins.
• Package F29: 29mm x 29mm package; 780 pins.
• Packages F34, F35, and F36: 35 mm x 35 mm package size; 1152 pins.
• Package F40: 40 mm x 40 mm package size; 1517 pins.
Device U19 F27 F29 F34 F35 F36 K F40 N F40
Transceiver Count, PCIe Hard IP Block Count
GX 016 6, 1 12, 1 12, 1
GX 022 6, 1 12, 1 12, 1
GX 027 12, 1 12, 1 24, 2 24, 2
GX 032 12, 1 12, 1 24, 2 24, 2
GX 048 12, 1 24, 2 36, 2
GX 057 24, 2 36, 2 36, 2 36, 2 48, 2
GX 066 24, 2 36, 2 36, 2 36, 2 48, 2
GX 090 24, 2 36, 2 48, 2
GX 115 24, 2 36, 2 48, 2
GT 090 48, 2
GT 115 48, 2
1-12
Arria 10 GX and GT Device Package Details
UG-01143
2015.05.11
Altera Corporation
Arria 10 Transceiver PHY Overview
Send Feedback