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Table 2-113: 10GBASE-KR Register Definitions
Word Addr Bit R/W Name Description
0x4B0
0
RW Reset SEQ When set to 1, resets the 10GBASE-KR sequencer
(auto rate detect logic), initiates a PCS reconfigura‐
tion, and may restart Auto-Negotiation, Link
Training or both if AN and LT are enabled
(10GBASE-KR mode). SEQ Force Mode[2:0]
forces these modes. This reset self clears.
1 RW Disable AN Timer Auto-Negotiation disable timer. If disabled
( Disable AN Timer = 1) , AN may get stuck and
require software support to remove the ABILITY_
DETECT capability if the link partner does not
include this feature. In addition, software may have
to take the link out of loopback mode if the link is
stuck in the ACKNOWLEDGE_DETECT state. To
enable this timer set Disable AN Timer = 0.
2 RW Disable LF Timer When set to 1, disables the Link Fault timer. When
set to 0, the Link Fault timer is enabled.
3 RW fail_lt_if_ber When set to 1, the last LT measurement is a non-
zero number. Treat this as a failed run. 0 = normal.
7:4 RW SEQ Force Mode[3:0]
Forces the sequencer to a specific protocol. Must
write the Reset SEQ bit to 1 for the Force to take
effect. The following encodings are defined:
• 0000: No force
• 0001: GigE
• 0010: XAUI
• 0100: 10GBASE-R
• 0101: 10GBASE-KR
• 1100: 10GBASE-KR FEC
8 RW Enable Arria 10
Calibration
When set to 1, it enables the Arria 10 HSSI reconfi‐
guration calibration as part of the PCS dynamic
reconfiguration. 0 skips the calibration when the
PCS is reconfigured.
16 RW KR FEC enable 171.0 When set to 1, FEC is enabled. When set to 0, FEC
is disabled. Resets to the CAPABLE_FEC
parameter value.
17 RW KR FEC enable err
ind 171.1
When set to 1, KR PHY FEC decoding errors are
signaled to the PCS. When set to 0, FEC errors are
not signaled to the PCS. See Clause 74.8.3 of IEEE
802.3ap-2007 for details.
18 RW KR FEC request When set to 1, enables the FEC request. When this
bit changes, you must assert the Reset SEQ bit
(0x4B0[0]) to renegotiate with the new value.
When set to 0, disables the FEC request.
UG-01143
2015.05.11
10GBASE-KR PHY Register Definitions
2-141
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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