User guide

Signal Name Direction Clock Domain Description
start_pcs_
reconfig
Input Synchronous to mgmt_
clk
When asserted, initiates reconfiguration of the
PCS. Sampled with the mgmt_clk. This signal is
only exposed under the following condition:
• Turn on Enable internal PCS reconfiguration
logic
mode_1g_
10gbar
Input Synchronous to mgmt_
clk
This signal selects either the 1G or 10G tx-parallel-
data going to the PCS. It is only used for the 1G/
10G application (variant) under the following
circumstances:
• the Sequencer (auto-rate detect) is not enabled
• 1G mode is enabled
Avalon-MM Register Interface
The Avalon-MM slave interface signals provide access to all registers.
Table 2-112: Avalon-MM Interface Signals
Signal Name Direction Clock Domain Description
mgmt_clk Input Clock The clock signal that controls the Avalon-MM PHY
management interface. If you plan to use the same
clock for the PHY management interface and
transceiver reconfiguration, you must restrict the
frequency to 100-125 MHz to meet the specification
for the transceiver reconfiguration clock.
mgmt_clk_reset Input Asynchronous
reset
Resets the PHY management interface. This signal is
active high and level sensitive.
mgmt_addr[10:0] Input Synchronous to
mgmt_clk
11-bit Avalon-MM address.
mgmt_
writedata[31:0]
Input Synchronous to
mgmt_clk
Input data.
mgmt_
readdata[31:0]
Output Synchronous to
mgmt_clk
Output data.
mgmt_write Input Synchronous to
mgmt_clk
Write signal. Active high.
mgmt_read Input Synchronous to
mgmt_clk
Read signal. Active high.
mgmt_
waitrequest
Output Synchronous to
mgmt_clk
When asserted, indicates that the Avalon-MM slave
interface is unable to respond to a read or write
request. When asserted, control signals to the
Avalon-MM slave interface must remain constant.
Related Information
Avalon Interface Specifications
UG-01143
2015.05.11
Avalon-MM Register Interface
2-139
Implementing Protocols in Arria 10 Transceivers
Altera Corporation
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